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課程說明及重點

高壓制程電子產(chǎn)品一般最大的可靠性問題是靜電放電(ESD) 很差、閂鎖(LU)能力也很差，而且模擬高壓電路輸出端口又會占很大面積，這會影響使其ESD能力通常非常不佳。ESD)/LU破壞是影響IC可靠性的重要因素也是延緩產(chǎn)品上市的主因，因此無論由制程上、設(shè)計上全方位的防護措施是必要的。本課程是高壓集成IC ESD/LU防護設(shè)計上之實務(wù)課程，更是各高壓集成IC產(chǎn)品ESD可靠度防護上最熱門的技術(shù)。

本課程將從各種HV CMOS元器件、晶圓廠技術(shù)平臺、HV組件的汲極工程、高壓元器件ESD/LU能力如何測試介紹起，進而談?wù)揌V CMOS 的各電性、可靠度缺點、晶圓廠HV ESD/LU 防護設(shè)計法則及各種ESD/LU保護策略及如何保護HV LDMOS與HV 集成電路ESD/LU防護實際案例分析，最后期許學員能對HV制程工藝及組件結(jié)構(gòu)充分理解，并熟悉HV IC靜電防護及LU免疫設(shè)計之防制意義。

授課對象

現(xiàn)職從事模擬IC與電子產(chǎn)品之RD設(shè)計、布局、制造、產(chǎn)品應用與品管、品保、FA相關(guān)技術(shù)人員 (對ESD/LU防護已有認識者)。

課程大綱

第一階段 :

I. High-Voltage CMOS Devices

◎ What’s an HV Technology ?

◎ How These Products Use the HV Process ?

◎ Foundry Technology Platform

II. Device Engineering for HV Devices

◎ Basic Concepts of an HV IC

◎ Well Engineerings

◎ Electrical Behaviors

III. HV ESD/LU Testing Issues

◎ How to Do an HV IC ESD Testing ?

◎ How to Do an HV IC Latch-up Testing ?

第二階段:

III. Weakness Issues in the HV CMOS Process

◎ High Resistive ESD Element Influence

◎ Intrinsic HV nMOS Reliability Problem

◎ Why ESD Level of the HV-CMOS I/O Protection Circuit is So Bad ?

◎ How About the Occurred Failure Mode in the HV CMOS ?

◎ HV Multi-Finger O/P nMOS Driver Protection Challenge

◎ Impact of Low-Holding-Voltage Issue in HV CMOS Technology

IV HV ESD/LU Rules (ex: 5V/30V/40V)

◎ Foundry HV ESD Design Rules

◎ Foundry HV LU Design Rules

V. Some Strategies of ESD/LU Protection Design in a HV CMOS Process

◎ How to Improve Low Vh ?

◎ How to Adjust Vt1 ?

◎ How to Guarantee That Vt2 >Vt1 ?

◎ How About the Single Finger Width Effect ?

◎ Which One Device Is More Better ?

◎ How About the N-Well Effect in a HV Drain Side ?

Day 3:

VI. How to Protect the HV LDMOS?

◎How to Do a Good ESD Immunity in the HV LDMOS?

◎ESD Protection Methods & Patents for the HV LDMOS

VII. (HV ESD/LU Cases Study)

VIII. Summary